1. Field of the Invention
The present invention relates to electrically rewritable semiconductor storage devices, and in particular, among these, to a non-volatile semiconductor storage device and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate. Although the dimension for each device must be reduced (refinement) to increase memory storage capacity, recent years are facing challenges in such refinement from the viewpoint of cost and technology. Such refinement requires further improvements in photolithography technology. However, in currently available ArF immersion lithography technology, for example, the resolution limit has been reached around the 40 nm design rule and so EUV exposure devices have to be introduced for further refinement. However, the EUV exposure devices are expensive and infeasible in view of the costs. In addition, if such refinement is accomplished, it is assumed that physical improvement limit, such as in breakdown voltage between devices, would be reached unless driving voltage can be scaled. Thus, it is likely that difficulties would be encountered in device operation itself.
Therefore, a large number of semiconductor storage devices have been proposed recently where memory cells are arranged in a three-dimensional manner to achieve improved integration of memory devices (see, Patent Document 1: Japanese Patent Laid-Open No. 2003-078044; Patent Document 2: U.S. Pat. No. 5,599,724; and Patent Document 3: U.S. Pat. No. 5,707,885).
One of the conventional semiconductor storage devices where memory cells are arranged in a three-dimensional manner uses transistors with an SGT (cylinder-type) structure (see, Patent Documents 1-3). Those semiconductor storage devices using transistors with the SGT structure are provided with multiple layers of polysilicon corresponding to gate electrode layers and pillar-like columnar semiconductors formed to penetrate the multiple layers of polysilicon. Each of the columnar semiconductors serves as a channel (body) part of each of the transistors. Charge accumulation layers are provided for accumulating charges around the columnar semiconductors via barrier insulation layers. In addition, block insulation layers are formed around the charge accumulation layers. Further, word-line conductive layers, which function as gate electrodes and expand in a two-dimensional manner, are formed around the block insulation layers. Such a configuration including polysilicon, columnar semiconductors, barrier insulation layers, charge accumulation layers, block insulation layers, and word-line conductive layers is referred to as a “memory string”.
This configuration, however, poses problems of larger parasitic capacitance involved between the word-line conductive layers because the word-line conductive layers are oppositely arranged to each other. In addition, if the word-line conductive layers are made thinner to ease the processing or to increase the number of laminated layers, then other problems arise in connection with an increase in resistance caused in the word-line conductive layers.
Due to the increase in parasitic capacitance and resistance in the word-line conductive layers caused by the foregoing problems, for example, when increasing the potential of the word-line conductive layers, a predetermined time difference for boosting voltage will exist between one ends of the word-line conductive layers to which voltage is applied from the plugs and the other ends spaced by a predetermined distance from the one ends. That is, a delay will be incurred in operation of the non-volatile semiconductor storage devices.